Pins can be individually configured, through the SENSE field in the PIN_CNF[n] register,to detect either a high level or a low level on their input.
When the correct level is detected on any such configured pin, the sense mechanism will set theDETECT signal high. Each pin has a separate DETECT signal, and the default behaviour, as definedby the DETECTMODE register, is that the DETECT signal from all pins in the GPIO Port are combinedinto a common DETECT signal that is routed throughout the system, which then can be utilized byother peripherals, see Figure 1.This mechanism is functional in both ON and OFF mode.
Figure 1. GPIO Port and the GPIO pin details
Figure 1 illustrates the GPIO port containing 32individual pins, where PIN0 is illustrated in more detail as a reference. Allthe signals on the left side of the illustration are used by other peripherals in the system, andtherefore, are not directly available to the CPU.
Make sure that a pin is in a level that cannot trigger the sense mechanism before enabling it.Detect will go high immediately if the sense condition configured in the PIN_CNF registers is metwhen the sense mechanism is enabled. This will trigger a PORT event if the DETECT signal was lowbefore enabling the sense mechanism. See GPIOTE — GPIO tasks and events.
See the following peripherals for more information about how the DETECT signal is used:
- POWER: uses the DETECT signal to exit from System OFF.
- GPIOTE: uses the DETECT signal to generate the PORT event.
When a pin's PINx.DETECT signal goes high, a flag will be set in theLATCH register, e.g. when the PIN0.DETECT signal goes high, bit 0 in the LATCH register will beset to '1'.
The LATCH register will only be cleared if the CPU explicitly clears itby writing a '1' to the bit that shall be cleared, i.e. the LATCH register will not beaffected by a PINx.DETECT signal being set low.
If the CPU performs a clear operation on a bit in the LATCH register whenthe associated PINx.DETECT signal is high, the bit in the LATCH register will not be cleared.
The LDETECT signal will be set high when one or more bits in the LATCHregister are '1'. The LDETECT signal will be set low when all bits in the LATCHregister are successfully cleared to '0'.
If one or more bits in the LATCH register are '1' after the CPUhas performed a clear operation on the LATCH registers, a rising edge will be generated on theLDETECT signal, this is illustrated in Figure 2.
Important: The CPU can read the LATCH register at any time tocheck if a SENSE condition has been met on one or more of the the GPIO pins even if thatcondition is no longer met at the time the CPU queries the LATCH register. This mechanism willwork even if the LDETECT signal is not used as the DETECT signal.
The LDETECT signal is by default not connected to the GPIO port'sDETECT signal, but via the DETECTMODE register it is possible to change the behaviour of the GPIOport's DETECT signal from the default behaviour described above to instead be deriveddirectly from the LDETECT signal, see Figure 1. Figure 2 illustrates the DETECT signalsbehaviour for these two alternatives.
Figure 2. DETECT signal behavior
The input buffer of a GPIO pin can be disconnected from the pin to enable power savings whenthe pin is not used as an input, see Figure 1. Inputsmust be connected in order to get a valid input value in the IN register and for the sensemechanism to get access to the pin.
Other peripherals in the system can attach themselves to GPIO pins and override their outputvalue and configuration, or read their analog or digital input value, see Figure 1.
Selected pins also support analog input signals, see ANAIN in Figure 1. The assignment of the analog pins can be foundin Pin assignments.
Important: When a pin is configured as digital input, care hasbeen taken in the nRF52832 design to minimize increased current consumption when the input voltageis between VIL and VIH. However, it is a good practice to ensure that theexternal circuitry does not drive that pin to levels between VIL and VIHfor a long period of time.
